The present invention relates to a nonvolatile, integrated-circuit memory array such as an electrically-erasable, electrically-programmable read-only-memory (EEPROM) array. In particular, the invention relates to a method for programming floating-gate memory cells.
EEPROMs using hot-carrier-injection programming, as opposed to Fowler-Nordheim tunneling programming, are described in: (a) "A Single Transistor EEPROM cell and its implementation in a 512K CMOS EEPROM," S. Mukherjee et al., IEDM 1985 (p. 616-619) and in (b) "A 90 ns 100K Erase/Program Cycle Megabit Flash Memory," V. Kynett et al., ISSCC 1989 (p. 140-141). The topic of reference (a) is also discussed in U.S. Pat. No. 4,698,787.
Using prior-art, hot-carrier-injection methods for programming, a reference voltage equal to the substrate voltage (Vss, which is perhaps 0 V) is applied to the source of the cell to be programmed, a first positive voltage Vdd, perhaps 6 V to 8 V, is applied to the drain, and a second positive voltage Vp1, perhaps 12 V, is applied to the control gate. Under those conditions, the channel between source and drain is highly conductive, the drain diffusion junction is reverse-biased with respect to the substrate (channel) while the source diffusion junction is not reverse-biased. Electrons reaching the drain diffusion are subjected to two electric fields, one associated with the reverse-biased drain diffusion junction and the other associated with the positive voltage coupled from the control gate to the floating gate. The electric fields cause electrons (hot carriers) to be injected into the floating gate.
One of the problems arising in flash EEPROMs is over-erasure of cells. An over-erased cell has a positive charge, causing the channel under the floating gate to be conductive. That over-erased conductive cell short circuits other cells in its column of parallel-connected cells. One method to compensate for over-erasure is to form the flash EEPROMs with split gates. Another method is to program all of the EEPROM cells, then apply light erasing pulses in steps, checking after each step to see whether or not all of the cells are erased. Other methods include applying alternating programming and erasing steps as described, for example, in U.S. Pat. No. 5,132,935 issued Jul. 21, 1992, and in U.S. Pat. No. 5,122,985 issued Aug. 16, 1992 and the references therein. Both patents relate to compaction, or narrowing, of the threshold voltage distributions of flash erased cells and both patents are assigned to Texas Instruments Incorporated.
One problem associated with prior-art flash EEPROMs has been a wide distribution of threshold voltages after a flash erase operation. The wide distribution is believed to be caused in part by trapped holes in the gate insulator or by injection of hot holes into the floating gate.
It is desirable to have a narrow distribution of threshold voltages after performing a flash erase procedure. In order to obtain the narrow distribution of erased threshold voltages, flash erase methods may require, as discussed above, at least one flash programming step before the final erase step to arrive at a final narrow distribution of erased threshold voltages.
At least two methods have been proposed to narrow or "compact" the distribution of programmed threshold voltages. Both of those methods are generally capable of raising the threshold voltages of cells having low voltage threshold voltages. One of those methods uses wordline stress to cause Fowler-Nordheim injection of electrons into the floating gate. The advantage of that method is that it is not limited by the magnitude of bitline leakage current. However, that method requires gate voltages higher than the normal programming voltage. Those higher gate voltages require, in turn, special fabrication steps to either lower the electric fields in the dielectric elements or strengthen those dielectric elements.
A second proposed method relies on hot-electron injection into the gate. This method is described in "A Self-Convergence Erasing Scheme for a Simple Stacked Gate Flash EEPROM", Yamada, et al., IEDM 1991 (p. 11.4.1-11.1.4). In the second method, the bitlines are biased at a voltage of 6-7 V and the sources are grounded (substrate voltage, or 0 V) while a low voltage (0-2 V) is applied to the control gates. While the voltages required by this approach are well within the circuit capability, the disadvantage of this second method is its requirement for large channel currents. That is, if there are several depleted cells connected to a drain-column line, that drain-column line may be over-loaded, thereby reducing programming capability. If the drain-column-line leakage is too large, the drain-column voltage collapses, causing the compaction procedure to fail. Also, using this second method (with sources grounded), hot holes may be injected into the gate thus increasing the drain-column-line leakage and defeating the purpose of the compaction.
A method for programming EPROMs using channel-hot electrons with sources biased at a positive voltage with respect to the substrate is described in U.S. Pat. No. 5,218,571 issued Jun. 8, 1993. In the method described in that patent, the control gates are biased at voltages equal to or greater than the threshold voltages of the EPROM cells.